Semiconductor storage device and read voltage correction method

ABSTRACT

A semiconductor memory device comprises a semiconductor memory, a corrected voltage storage circuit which stores a corrected voltage produced by correcting a read voltage of the semiconductor memory, and a memory controller which reads the corrected voltage from the corrected voltage storage circuit and performs a read operation of the semiconductor memory using the corrected voltage.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromprior Japanese Patent Application No. 2006-241806, filed Sep. 6, 2006,the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a semiconductor storage device and a readvoltage correction method for use with the storage device, which is, forexample, a NAND type flash memory.

2. Description of the Related Art

Evaluation of the read disturb characteristic of NAND type flashmemories (chips) on the same semiconductor wafer using the same readvoltage reveals that the measurement of the read disturb characteristicvaries from chip to chip (see, for example, JP-A 2002-016154 (KOKAI);corresponding to U.S. Pat. No. 6,933,914). This is expected to beattributed to memory characteristic variations resulting from variousvariations in processing during the manufacturing process. With the NANDtype flash memories in particular, the coupling ratio and the neutralthreshold of memory cells greatly affect the electric field strength inthe tunnel insulating film when a read voltage (Vread) is being applied,which has a great influence upon the read disturb characteristic. Thus,the amounts of leakage current which occurs when the same read voltageis applied depend greatly upon these and influence the read disturbcharacteristic.

Thus, setting the read voltage Vread to a value common to all thesemiconductor chips of a semiconductor wafer gives rise to variations inthe amount of leakage current in the tunnel insulating film due tovariations in the coupling ratio and neutral threshold, causing the readdisturb characteristic to vary from chip to chip.

On the other hand, with present-day manufacturing process technology, itis practically impossible to obtain such precision that influence onvariations in read disturb characteristic can be neglected.

With the conventional semiconductor storage devices, as described above,a read operation is performed on the basis of a common read voltageVread. That is, no read operation is performed using a read voltagecorrected so that the read disturb characteristic is optimized for eachsemiconductor chip. For this reason, the read disturb characteristic isnot optimized and the number of fail bits increases, lowering thereliability.

In addition, in the conventional method of examination of semiconductorstorage devices, the read voltage Vread is not corrected for eachsemiconductor chip so as to optimize the read disturb characteristic ofeach semiconductor chip.

For this reason, when a fixed common read voltage is used for all thesemiconductor chips in a semiconductor wafer, faulty chips which fail tomeet the standard read disturb characteristic increase in number andproper chips obtained from the wafer decrease in number, lowering themanufacturing yield.

BRIEF SUMMARY OF THE INVENTION

According to an aspect of the invention, there is provided asemiconductor storage device comprising: a semiconductor memory; acorrected voltage storage circuit which stores a corrected voltageproduced by correcting a read voltage of the semiconductor memory; and amemory controller which reads the corrected voltage from the correctedvoltage storage circuit and performs a read operation of thesemiconductor memory using the corrected voltage.

According to another aspect of the invention, there is provided a readvoltage correction method for use with a semiconductor storage deviceequipped with a reference chip and a to-be-corrected chip which has acorrected voltage storage circuit, comprising: obtaining a write voltageof the to-be-corrected chip; obtaining an erase voltage of theto-be-corrected chip; and correcting a read voltage of theto-be-corrected chip in accordance with the write and erase voltagesobtained.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a plan view of a semiconductor storage device according to anembodiment of the present invention;

FIG. 2A shows an example of a circuit diagram of the corrected voltagestorage circuit in FIG. 1;

FIG. 2B shows another example of a circuit diagram of the correctedvoltage storage circuit in FIG. 1;

FIG. 3 shows a circuit arrangement of the NAND type flash memory in FIG.1;

FIG. 4 is a sectional view of a column of NAND cells in a read operationof the semiconductor storage device according to the embodiment;

FIG. 5 shows the read disturb characteristic of the semiconductorstorage device according to the embodiment;

FIG. 6 is a sectional view for use in explanation of the read disturbcharacteristic;

FIG. 7 is a diagram for use in explanation of the read disturbcharacteristic;

FIG. 8 shows the read disturb characteristic;

FIG. 9 shows the read disturb characteristics of different semiconductorchips obtained from the same silicon wafer;

FIG. 10 is a plan view for use in explanation of a read voltagecorrection method for use with the semiconductor storage deviceaccording to the embodiment;

FIG. 11 is a diagram for use in explanation of the read voltagecorrection method for use with the semiconductor storage deviceaccording to the embodiment;

FIG. 12 is a flowchart for use in explanation of the read voltagecorrection method according to the embodiment;

FIG. 13A shows values required with the read voltage correction methodaccording to the embodiment;

FIG. 13B shows values required with the read voltage correction methodaccording to the embodiment;

FIG. 14 shows one step in the read voltage correction method accordingto the embodiment;

FIG. 15 shows one step in the read voltage correction method accordingto the embodiment; and

FIG. 16 shows the read disturb characteristic after the read voltagecorrection method according to the embodiment has been performed.

DETAILED DESCRIPTION OF THE INVENTION

An embodiment of the present invention will be described hereinafterwith reference to the accompanying drawings. In the description whichfollows, like reference characters are used to designate like orcorresponding parts throughout the drawings.

First, reference is made to FIGS. 1 through 3 to describe thearrangement of a semiconductor storage device according to an embodimentof the present invention. FIG. 1 is a plan view of the semiconductorstorage device of this embodiment. FIG. 3 shows a circuit arrangement ofthe NAND type flash memory in FIG. 1.

As shown, a semiconductor chip 11 contains a NAND type flash memory 12,a corrected voltage storage circuit 19, and a memory controller 13.

The NAND type flash memory 12 has memory cell arrays 14 each of whichhas memory cell transistors MT arranged in the form of an array, rowdecoders 15 which select the memory cell arrays 14, and a peripheralcircuit 16 equipped with sense amplifiers and the like. The NAND typeflash memory 12 may be configured as an SLC (Single Level Cell) which iscapable of recording 1-bit data in one memory cell transistor MT, or anMLC (Multi Level Cell) that is capable of recording multi-bit data inone memory cell transistor MT.

The corrected voltage storage circuit 19 is set in the peripheralcircuit 16 of the NAND type flash memory 12 and configured to store acorrected voltage (Vread′). The corrected voltage Vread′ is a readvoltage in which the read voltage (Vread) of the NAND type flash memory12 has been corrected according to a method to be described later. In aread operation, the corrected voltage Vread′ is read by the memorycontroller 13 over an interconnect line 17-2.

As the corrected voltage storage circuit 19, use may be made of acircuit having a memory cell of a flash memory or ferroelectric memory(FeRAM: Ferroelectric Random Access Memory) which has its current pathconnected at one end to the memory controller 13 as shown in FIGS. 2Aand 2B. In addition, a part of the memory cell array 14 may also be usedas the flash memory to reduce the area of the circuit. Alternatively,the corrected voltage storage circuit may be formed of an SRAM (StaticRandom Access Memory) or MRAM (Magnetic Random Access Memory) memorycell to store the corrected voltage Vread′.

The memory controller 13 is configured to control the internal physicalstates of the NAND type flash memory 12 (e.g., which logical sectoraddress data is contained in which physical block addresses, or whichblock is in erased state), and, in a read operation, to read thecorrected voltage Vread′ from the corrected voltage storage circuit 19and read from the NAND type flash memory 12 using the corrected readvoltage Vread′. In addition, the controller 13 performs datainput/output control and data management on the flash memory 12, addserror correction codes (ECC) upon writing, and analyzes the errorcorrection codes upon reading.

Next, the exemplary arrangement of the NAND type flash memory 12 will bedescribed with reference to FIG. 3. As shown, the NAND flash memory 12is equipped with the row decoder 15, the memory cell array 14, a senseamplifier 24, and a source line driver 25.

The row decoder 15 is configured to select word lines WL1 to WL8 andselect gate lines SGD and SGS in accordance with an address from anaddress buffer (not shown). The row decoder 15 has a row main decodercircuit 26 and a core unit (row sub-decoder circuit) 27.

The row main decoder circuit 26 decodes a row address signal to send arow address decoded signal to the core unit 27. The core unit 27 isequipped with transfer gate transistors TGTD and TGTS and transfertransistors TR1 to TR8, which have their gates connected together to atransfer gate line TG.

The memory cell array 14 is equipped with NAND cell columns 28 each ofwhich is composed of select transistors ST1 and ST2 and memory celltransistors MT1 to MT8 which have their current paths connected inseries. The transistors in the memory cell array are arranged in amatrix form. One end of the series-connected current paths of thetransistors is connected to the sense amplifier 24 and the other end isconnected to a source line SL.

Each of the memory cell transistors MT1 to MT8 is a stacked structurehaving a tunnel insulating film formed on a semiconductor substrate, afloating gate FG formed on the tunnel insulating film, an intergateinsulating film formed on the floating gate, and a control gate CGformed on the intergate insulating film. The memory cell transistor MT1to MT8 are arranged to adjoin one another along the direction of bitlines so that adjacent transistors share their source and drain.

The number of the memory transistors MT is not limited to eight as inthis example but may be 16, 32, etc. One of the paired selecttransistors ST1 and ST2 may be omitted provided that the correspondingNAND cell column 28 can be selected.

The control gates CG of the memory cell transistors MT in the same rowin the direction of word lines orthogonal to the direction of bit linesare connected together at one of the word lines WL1 to WL8. The gates ofthe select transistors ST1 and ST2 in the same column in the directionof word lines are connected commonly to either of the select gates SGDand SGS, respectively. The drain of each of the select transistors ST1is connected to a respective one of the bit lines BL1 to BLn. Thesources of the select transistors ST2 are connected together to thesource line SL, which is in turn connected to the source line driver 25.

The sense amplifier 24 is arranged in the peripheral circuit 16 andconfigured to amplify data read from a selected memory cell transistorMT.

The source line driver 25 is set in the peripheral circuit 16 andconfigured to apply a source voltage to the source line SL.

[Read Operation]

The read operation of the semiconductor storage device of thisembodiment will be described next with reference to FIGS. 3 to 5. Theread operation of the NAND type flash memory 12 is performed on a wordline basis (on a page-by-page basis); however, to simplify thedescription, reading from the memory cell transistor MT3 will bedescribed here as an example. FIG. 4 is a schematic sectional view ofthe NAND cell column 28 in this read operation.

First, as shown in FIG. 3, the memory controller 13 reads the correctedvoltage Vread′ from the corrected voltage storage circuit 19.

Next, the memory controller 13 controls the row decoder 15, the sourceline driver 25, and the sense amplifier 24 so that potentials shown inFIG. 4 are applied to the memory cell array 14.

That is, the row decoder 15 drives the transfer transistors TR1 to TR8so that the corrected voltage Vread′ is applied to the control gates CGof the nonselected memory cell transistors MT1, MT2, and MT4 to MT8 and0 volts (predetermined potential) are applied to the control gate of theselected memory cell transistor MT3. The row decoder 15 drives thetransfer gate transistors TGTD and TGTS so that a voltage Vsg to turn onthe select transistors ST1 and ST2 is applied to the gate electrodes G1and G2 of the select transistors ST1 and ST2. The source line driver 25is controlled to apply 0 volts to the source S/D of the selecttransistor ST1 and the sense amplifier 24 is controlled to apply avoltage Vb1 to the drain of the select transistor ST1.

According to the condition of the charges stored at the float gate inthe selected memory cell transistor MT3, the memory cell transistor isturned on or turned off. As a result, the channels CH of the nonselectedmemory cell transistors MT1, MT2 and MT4 to MT8 are rendered conductiveby the corrected voltage Vread′ and, according to the ON/OFF conditionof the selected memory cell transistor MT3, electric current passingthrough the conductive channels CH is varied. As a result, the senseamplifier 24 detects occurrence of the variation in the sense nodestored in the capacity of the sense amplifier 24, thereby completing theread operation.

As described above, the row decoder 15 drives the transfer transistorsTR1, TR2, and TR4 to TR8 so that the corrected voltage Vread′ is appliedto the control gates CG of the nonselected memory cell transistors MT1,MT2, and MT4 to MT8.

For this reason, as shown in FIG. 5, the read disturb characteristic RD′can be improved. In FIG. 5, a solid line RD′ indicates the read disturbcharacteristic based on the corrected voltage Vread′ in this example,whereas a broken line RD represents the read disturb characteristicbased on a non-corrected read voltage.

As shown, the solid line RD′ when a read operation is performed usingthe corrected voltage Vread′ lies below the broken line RD at any time;therefore, it can be seen that the number of fail bits can be reduced.For example, at time 10³ [s], about 1000 fail bits can be reduced asindicated by the difference 55.

Thus, the read disturb characteristic RD′ can be improved and the numberof fail bits can be reduced. Therefore, the reliability of the NAND typeflash memory 12 is increased.

Here, the read disturb characteristic will be described with referenceto FIGS. 6 to 9.

As described above, in a read operation, it is required to turn onnonselected memory cell transistors by applying a read voltage ontononselected word lines.

As shown in FIG. 6, at this point, the read voltage applied to thetunnel insulating films of the nonselected memory cell transistors cancause electrons to leak from the substrate to the floating electrodesFG, thereby causing weak writing to occur. As a result, the thresholdvoltages of the nonselected memory cell transistors rise and data changeoccurs, which leads to read disturb.

The cells which are faster in threshold rise are defined to be poor inthe read disturb characteristic and appear as the base of a distributionby continuing the read operation. For example, FIG. 8 shows therelationship between the total number of fail bits and the time(Tstress) with cells having their threshold voltages increased above acertain threshold voltage Vth as fail bits. As shown, although thethreshold voltage distribution exhibits a normal distribution at timeT0, the cells the threshold voltage rise increase with the lapse of timefrom T1 to T2.

As shown in FIG. 8, the read disturb characteristic is obtained from therelationship between the time (Tstress) and the number of memory celltransistors having threshold voltages increased above a certain value(the number of fail bits). The lower the characteristic line lies belowthe Y axis, the better the characteristic is.

FIG. 9 shows read disturb characteristics of separate semiconductorchips obtained from the same silicon wafer. For example, FIG. 9, evenwith semiconductor chips obtained from the same silicon wafer,variations occur in the read disturb characteristic due to variousvariations in processing in the manufacturing process. For example,variations include variations in the thickness of the tunnel insulatingfilm 35 and variations in the shape of the control electrode CG shown inFIG. 6. The read disturb characteristic indicated by solid line 57 liesabove the characteristic indicated by solid line 58, exhibiting that theformer is poorer than the latter.

In this embodiment, however, as shown in FIG. 5, the characteristic lineRD′ when a read operation is performed using the corrected voltageVread′ lies below the characteristic line RD at any time, thus allowingthe number of fail bits to be reduced. Thus, the embodiment hasadvantages in that the read disturb characteristic can be improved, thenumber of fail bits can be reduced, and the reliability can be increasedirrespective of variations in processing in the manufacturing process.

[Read Voltage Correction Method]

Next, the read voltage correction method for use with the semiconductorstorage device according to this embodiment will be described withreference to FIGS. 10 to 16. The correction method of this embodimentinvolves, to improve the read disturb characteristic, making apredetermined correction to a read voltage to determine a correctedvoltage Vread′ for each semiconductor chip and then storing thiscorrected voltage into the corresponding corrected voltage storingcircuit 19.

FIG. 10 is a plan view illustrating a large number of NAND type flashmemories 12 formed on a silicon wafer 10 before dicing.

As shown, the controller 13 is not yet incorporated into the chip. Inthis state, the read voltage correction is made.

Here, a description is given with a NAND type flash memory 12-0 as areference chip CHIP(A) for this correction method and a NAND type flashmemory which is an object of correction as a to-be-corrected chip CHIP(B). Although, in this example, the reference chip CHIP(A) and theto-be-corrected chip CHIP(B) are described as semiconductor chips formedon the same silicon wafer, they may be ones formed on separate siliconwafers.

As shown in FIG. 11, required values in this description are detected bya probe 32 electrically connected to the NAND type flash memory 12-1 andprocessed and displayed by a tester 31. FIG. 11 shows the state in whichthe required values are detected from the to-be-corrected chip CHIP(B).The read voltage correction method of this embodiment is performed inaccordance with steps ST1 to ST4 shown in FIG. 12.

FIGS. 13A and 13B show values required with the correction method. FIG.13A shows the required values for the reference chip CHIP(A). FIG. 13Bshows the required values for the to-be-corrected chip CHIP(B). Of thevalues shown, values to be measured are the write voltage Vpgm0 and theerase voltage Verase0 of the to-be-corrected chip CHIP(B). The othervalues are determined by calculations using expressions to be describedlater.

[Step ST1]

First, as shown in FIG. 14, a write operation is performed on aconsiderable number of memory cell transistors MT (e.g., of the order ofseveral megabits) and the distribution of their threshold voltages Vthis processed and displayed by the tester 31. The write voltage Vpgm0 ofthe to-be-corrected chip CHIP(B) is then obtained from the analysis ofthe maximum value (Vthw peak) in the distribution.

[Step S2]

Then, as shown in FIG. 15, an erase operation is performed on aconsiderable number of memory cell transistors MT and the distributionof their threshold voltages Vth is processed and displayed by the tester31. The erase voltage Verase0 of the to-be-corrected chip CHIP(B) isthen obtained from the analysis of the maximum value (Vthe peak) in thedistribution.

[Step ST3]

Next, the corrected voltage Vread′ is calculated according to thefollowing expressions using the write voltage Vpgm0 and the erasevoltage Verase0 of the to-be-corrected chip CHIP(B) thus obtained.

First, the floating gate voltage Vfg of the reference chip CHIP(A) isexpressed by

Vfg=Cγ(Vcg−Vth+Vt0)  (*)

where Cγ is the coupling ratio of the reference chip CHIP(A), Vcg is thegate potential of the reference chip CHIP(A), Vth is the cell thresholdpotential, and Vt0 is the cell neutral threshold of the reference chipCHIP(A). Designed values can be used as the coupling ratio, the cellthreshold potential and the cell neutral threshold. If more exact valuesare needed, they can be obtained by measuring TEG (TEST ELEMENT GROUP)of the memory cell transistor. The coupling ratio indicates a ratio ofthe voltage applied to the tunnel insulation film, of the voltagesapplied to the control gate

On the other hand, the floating gate voltage Vfg′ of the to-be-correctedchip CHIP(B) is expressed as follows:

Vfg′=Cγ′(Vcg′−Vth+Vt0′)  (**)

where Cγ′ is the coupling ratio of the to-be-corrected chip CHIP(B),Vcg′ is the gate potential of the to-be-corrected chip CHIP(B), Vth isthe cell threshold potential, and Vt0′ is the cell neutral threshold ofthe to-be-corrected chip CHIP(B). Similarly to the reference chip (A),values obtained by measuring TEG are used as the coupling ratio, thecell threshold potential and the cell neutral threshold.

If it is known here that the to-be-corrected chip CHIP(B) is higher inneutral threshold than the reference chip CHIP(A) by a. When, the cellneutral threshold Vt0′ of the to-be-corrected chip CHIP(B) and α arerelated by

Vt0′=Vt0+α

Using the write voltage Vpgm and the erase voltage Verase of thereference chip CHIP(A) and the write voltage Vpgm0 and the erase voltageVerase0 of the to-be-corrected chip CHIP(B), α is expressed by

α=(Vpgm0+Verase0)/2−(Vpgm+Verase)/2

Using the coupling ratio coefficient β, the coupling ratio Cγ′ of theto-be-corrected chip CHIP(B) is expressed by

Cγ′=β×Cγ

The coupling ratio coefficient β is expressed by

β=100×[{(Vpgm−Verase)−(Vpgm0−Verase0)}]/2/Vpgm

From the above expressions, the gate voltage Vcg′ of the to-be-correctedchip CHIP(B) is calculated as follows:

Vcg′=(Cγ′÷Cγ)×Vcg+(Vt−Vt0)×{1−(Cγ′÷Cγ)}−α

From the above, the corrected voltage Vread′ of the to-be-corrected chipCHIP(B) can be determined by

Vread′=(Cγ′÷Cγ)×Vread+(Vt−Vt0)×{1−(Cγ′÷Cγ)}

[Step T4]

Next, the corrected voltage Vread′ thus determined is stored in thecorrected voltage storage circuit 19 in the to-be-corrected chipCHIP(B).

The read voltage correction method for use with the semiconductorstorage device according to this embodiment offers at least thefollowing advantages (1) and (2):

(1) The manufacturing yield can be improved.

As described above, the correction method of this embodiment involvesobtaining the write voltage Vpgm0 and the erase voltage Verase0 of theto-be-corrected chip CHIP(B), determining the corrected voltage Vread′of the chip CHIP(B) according to the above calculations, and storing thecorrected voltage in the corrected voltage storage circuit 19 of thechip CHIP(B).

Therefore, the read disturb characteristic RD(B)′ of the to-be-correctedchip CHIP(B) can be improved as shown in FIG. 16. In this figure, thesolid line RD(B) indicates the read disturb characteristic of theto-be-corrected chip CHIP(B) based on the corrected voltage Vread′,whereas the broken line RD(B) indicates the read disturb characteristicof the to-be-corrected chip CHIP(B) based on a read voltage beforecorrection. The solid line RD(A) indicates the read disturbcharacteristic of the reference chip CHIP(A).

As shown, the solid line RD(B) lies close to the solid line RD(A)indicating the read disturb characteristic of the reference chipCHIP(A). It can be seen that, with the solid line RD(B)′, the number offail bits is less than that with the broken line RD(B) at any time.

On the other hand, the conventional examination of the read disturbcharacteristic has been made by performing a read operation using acommon read voltage Vread. For this reason, the number of faulty chipswhich do not meet a standard read disturb characteristic (for example,chips having the read disturb characteristic indicated by the brokenline RD(B) in FIG. 16) increases and hence the number of appropriatechips which can be obtained from a silicon wafer decreases; thus, themanufacturing yield tends to lower.

In this embodiment, however, the corrected voltage Vread′ that optimizesthe read disturb characteristic can be calculated for each chip.Therefore, even chips which would be treated as faulty chips if a commonread voltage Vread were used can be corrected as available proper chips(for example, corrected chips CHIP(B) having the read disturbcharacteristic indicated by the solid line (RD(B) in FIG. 16).

For this reason, the number of appropriate chips which can be obtainedfrom a semiconductor wafer can be increased, allowing the manufacturingyield to be increased.

(2) An increase in manufacturing cost can be suppressed.

With the method of this embodiment, in examining the read disturbcharacteristic it is only necessary to obtain required values throughthe use of the probe 32 and the tester 31 and perform givencalculations. For this reason, there is no need of using high-accuracyexposure equipment that suppresses variations in the cell shape ofmemory cell transistors MT and the read disturb characteristic can beimproved without changing the manufacturing process, which is effectivein suppressing an increase in manufacturing cost. It is more effectivein suppressing the increase in manufacturing cost, by adding theexamination of the read disturb characteristic in examinations of theelectric characteristics prior to dicing.

For example, the introduction of high-accuracy exposure equipment ofshorter wavelengths would involve a manufacturing cost of the order ofhundreds of millions of yen. If the number of photomasks were increasedwith changes in manufacturing process, a manufacturing cost of the orderof millions of yen would be involved for each mask. However, theembodiment can provide the same advantages without involving suchmanufacturing costs.

In addition, at the time of examination, the correction method of thisembodiment simply obtains the write voltage Vpgm0 and the erase voltageVerase0 of an object chip and performs predetermined calculations;therefore, the examination time will not be increased.

The embodiment has been described in terms of a semiconductor chip whichcontains a corrected voltage storage circuit to store a corrected readvoltage and a read voltage correction method for use with thatsemiconductor chip. However, even with a semiconductor chip equippedwith a corrected voltage storage circuit that stores a corrected writevoltage, the same advantages could be obtained.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1. A semiconductor storage device comprising: a semiconductor memory; acorrected voltage storage circuit which stores a corrected voltageproduced by correcting a read voltage set by a reference semiconductormemory of the semiconductor memory; and a memory controller which readsthe corrected voltage from the corrected voltage storage circuit andperforms a read operation of the semiconductor memory using thecorrected voltage.
 2. The device according to claim 1, furthercomprising an interconnect line which electrically connect the correctedvoltage storage circuit to the controller, and wherein, in a readoperation, the corrected voltage is read from the corrected voltagestorage circuit over the interconnect line by the memory controller. 3.The device according to claim 1, wherein the corrected voltage storagecircuit includes a memory cell to store the corrected voltage.
 4. Thedevice according to claim 3, wherein the memory cell is a memory celltransistor which has its current path electrically connected at one endto the memory controller.
 5. The device according to claim 3, whereinthe memory cell is a ferroelectric memory transistor which has itscurrent path electrically connected at one end to the memory controller.6. The device according to claim 1, wherein the corrected voltagestorage circuit is placed in a peripheral circuit of the semiconductormemory.
 7. The device according to claim 1, wherein the semiconductormemory has a memory cell array, a row decoder, a sense amplifier, and asource line driver.
 8. The device according to claim 7, wherein thememory cell array has a plurality of memory cells arranged in the formof a matrix at intersections of word lines and bit lines, and thecontroller controls the memory cell array so that, in a read operation,the corrected voltage is applied to nonselected memory cells and apredetermined voltage is applied to a selected memory cell.
 9. Thedevice according to claim 1, wherein the semiconductor memory is a NANDtype flash memory.
 10. The device according to claim 1, wherein, whenthe storage device is taken as a to-be-corrected semiconductor memorythe read voltage of which is to be corrected by referring to thereference semiconductor memory, the corrected voltage is given by(Cγ′÷Cγ)×Vread+(Vt−Vt0)×{1−(Cγ′÷Cγ)} wherein Cγ′ is the coupling ratioof the corrected semiconductor memory, Cγ is the coupling ratio of thereference semiconductor memory, Vread is the read voltage of thecorrected semiconductor memory before correction, Vt is the thresholdvoltage of memory cells of the reference semiconductor memory, and Vt0is the neutral threshold voltage of the memory cells of the referencesemiconductor memory.
 11. The device according to claim 9, wherein, whenthe storage device is taken as a to-be-corrected semiconductor memorythe read voltage of which is to be corrected by referring to thereference semiconductor memory, the corrected voltage is given by(Cγ′÷Cγ)×Vread+(Vt−Vt0)×{1−(Cγ÷Cγ)} wherein Cγ′ is the coupling ratio ofthe corrected semiconductor memory, Cγ is the coupling ratio of thereference semiconductor memory, Vread is the read voltage of thecorrected semiconductor memory before correction, Vt is the thresholdvoltage of memory cells of the reference semiconductor memory, and Vt0is the neutral threshold voltage of the memory cells of the referencesemiconductor memory.
 12. The device according to claim 1, wherein thesemiconductor memory and the reference semiconductor memory are formedon a same wafer.
 13. The device according to claim 10, wherein thecoupling ratio of the reference semiconductor memory, the thresholdvoltage of memory cells of the reference semiconductor memory, and theneutral threshold voltage of the memory cells of the referencesemiconductor memory, are obtained by measuring TEG.
 14. A read voltagecorrection method for use with a semiconductor storage device equippedwith a reference semiconductor memory and a to-be-correctedsemiconductor memory which has a corrected voltage storage circuit,comprising: obtaining a write voltage of the to-be-correctedsemiconductor memory; obtaining an erase voltage of the to-be-correctedsemiconductor memory; and correcting a read voltage of theto-be-corrected semiconductor memory in accordance with the write anderase voltages obtained.
 15. The method according to claim 14, furthercomprising storing the corrected read voltage into the corrected voltagestorage circuit of the to-be-corrected semiconductor memory.
 16. Themethod according to claim 14, wherein the corrected read voltage isgiven by(Cγ′÷Cγ)×Vread+(Vt−Vt0)×{1−(Cγ÷Cγ)} wherein Cγ′ is the coupling ratio ofthe to-be-corrected semiconductor memory, Cγ is the coupling ratio ofthe reference chip, Vread is the read voltage of the to-be-correctedsemiconductor memory before correction, Vt is the threshold voltage ofmemory cells of the reference semiconductor memory, and Vt0 is theneutral threshold voltage of the memory cells of the referencesemiconductor memory.
 17. The method according to claim 14, wherein thefloating gate potential Vfg of the reference semiconductor memory isexpressed byVfg=Cγ(Vcg−Vth+Vt0) where Vcg is the gate potential of the referencesemiconductor memory, and Vth is the cell threshold potential.
 18. Themethod according to claim 14, wherein the floating gate potential Vfg′of the to-be-corrected semiconductor memory is expressed byVfg′=Cγ′(Vcg′−Vth+Vt0′) where Cγ′ is the coupling ratio of theto-be-corrected semiconductor memory, Vcg′ is the gate potential of theto-be-corrected semiconductor memory, Vth is the cell thresholdpotential, and Vt0′ is the cell neutral threshold of the to-be-correctedsemiconductor memory.
 19. The method according to claim 14, whereinvalues necessary for the correction method are detected by a probe whichis electrically connected to the reference semiconductor memory or theto-be-corrected semiconductor memory and then processed and displayed bya tester.
 20. The method according to claim 19, wherein an examinationof read disturb characteristic is added to examinations of electriccharacteristics prior to dicing.